Embodiments of the present invention relate generally to the fabrication of semiconductor devices, and more particularly to metal-insulator-metal capacitors (MIM capacitors).
Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. Integrated circuits typically include multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. Many integrated circuits now include multiple levels of metallization for interconnections.
Capacitors are elements that are used extensively in semiconductor devices for storing an electrical charge. Capacitors essentially comprise two conductive plates separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, is measured in farads and depends upon a number of parameters such as the area of the plates, the distance between the plates, and the dielectric constant value for the insulator between the plates, as examples. Capacitors are used in filters, analog-to-digital converters, memory devices, control applications, and many other types of semiconductor devices.
One type of capacitor is a metal-insulator-metal capacitor (MIM capacitor), which is used often in mixed signal devices and logic devices, for example. MIM capacitors are used to store a charge in a variety of semiconductors. MIM capacitors typically require a much lower capacitance than deep trench memory capacitors, for example. A MIM capacitor may have a capacitance requirement of 1 fF/micrometer2, for example. A MIM capacitor is typically formed horizontally on a semiconductor wafer, with two metal plates sandwiching a dielectric parallel to the wafer surface. At least one of the metal plates is usually formed in a metallization layer (metal interconnect layer) of the device. MIM capacitors embedded in the back-end-of-line (BEOL) structures have been used in many very large scale integrated logic (VLSI) devices in the past.
Horizontal MIM capacitors are manufactured in the BEOL, a stage in semiconductor device fabrication that usually begins with the formation of the first metallization layer on the wafer. MIM capacitors are typically formed in the BEOL by forming a bottom capacitive plate in a first or subsequently deposited horizontal metallization layer of a semiconductor wafer using a first lithography mask. A first etch step such as a reactive ion etch (RIE) is used to transfer the mask pattern to the bottom plate. A capacitor dielectric is deposited over the bottom capacitive plate, and a second mask and RIE step is used to pattern the capacitor dielectric. A top capacitive plate material is deposited over the capacitor dielectric, and a third mask and RIE step is used to form the top capacitive plate. Each mask and RIE step adds labor and cost to the MIM capacitor fabrication process.
Embodiments of the present invention achieve technical advantages as a method of forming MIM capacitor structures that requires only one mask. The method includes a process for fabricating MIM capacitors embedded in dual-damascene BEOL structures with high capacitance density. A single horizontal MIM capacitor or a plurality of parallel horizontal MIM capacitors may be fabricated in a dual damascene structure in accordance with embodiments of the invention.
In accordance with a preferred embodiment of the present invention, a method of forming a MIM capacitor includes providing a workpiece, depositing an inter-level dielectric (ILD) layer over the workpiece, and forming a first pattern in the ILD layer, wherein the first pattern has a first depth within the ILD layer. A second pattern is formed in the ILD layer, the second pattern having a second depth within the ILD layer. The second depth is greater than the first depth. A first conductive layer is disposed over the first pattern of the ILD layer. A second conductive layer is disposed over the second pattern of the ILD layer, and a first dielectric layer is disposed over at least the second conductive layer. A third conductive layer is disposed over the first dielectric layer. The second conductive layer, first dielectric layer and third conductive layer over the second pattern form a first MIM capacitor.
In accordance with another preferred embodiment of the present invention, a MIM capacitor includes a workpiece and an ILD layer deposited over the workpiece. The ILD layer includes a first pattern having a first depth and a second pattern having a second depth, with the second depth being greater than the first depth. A first conductive layer is disposed over the first pattern of the ILD layer. A second conductive layer is disposed over the second pattern of the ILD layer, a first dielectric layer is disposed over the second conductive layer, and a third conductive layer is disposed over the first dielectric layer. The second conductive layer, first dielectric layer and third conductive layer over the ILD layer second pattern form a first MIM capacitor.
Advantages of embodiments of the invention include providing a simplified process for forming a MIM capacitor in a semiconductor device. The two-depth structure of a dual damascene process is utilized, forming a MIM capacitor in the deeper via portion of the ILD layer, while conductive lines are simultaneously formed in the shallower metallization layer. Only one mask is required to form a single MIM capacitor or multiple parallel MIM capacitors, resulting in production time, cost and labor savings. A planarization step is used to form the MIM capacitor structure within the MIM capacitor pattern of the ILD or dielectric layer. Parallel MIM capacitors may be connected in parallel, increasing the capacitance of the MIM capacitor structure.